How to include clean target in makefile?

In makefile language $ means "name of the target", so rm -f $ translates to rm -f clean.

In makefile language $@ means "name of the target", so rm -f $@ translates to rm -f clean. You need to specify to rm what exactly you want to delete, like rm -f *. O code1 code2.

The best thing is probably to create a variable that holds your binaries: binaries=code1 code2 Then use that in the all-target, to avoid repeating: all: clean $(binaries) Now, you can use this with the clean-target, too, and just add some globs to catch object files and stuff: . PHONY: clean clean: rm -f $(binaries) *. O Note use of the .

PHONY to make clean a pseudo-target. This is a GNU make feature, so if you need to be portable to other make implementations, don't use it.

2 +1 for . PHONY (which is a GNU-ism, but Mostly Harmless elsewhere). However, it's a bad idea to put clean as a dependency of all; that increases build time and noise.

Better to define all the real dependencies so that changes to source get propagated exactly as far as necessary. – Donal Fellows Apr 14 '10 at 8:46.

By the way it is written, clean rule is invoked only if it is explicitly called: make clean I think it is better, than make clean every time. If you want to do this by your way, try this: CXX = g++ -O2 -Wall all: clean code1 code2 code1: code1. Cc utilities.Cc $(CXX) $^ -o $@ code2: code2.

Cc utilities. Cc $(CXX) $^ -o $@ clean: rm ... echo Clean done.

As qrdl explained, this is wrong. "rm -f $@" becomes "rm -f clean", which would not work. – bjarkef Apr 14 '10 at 7:24 No downvote, but usually this is a bad idea.

Anything but a very small project takes some time to build from scratch, and you really don't want to have to wait that long every time you have made a small change. – Thomas Padron-McCarthy Apr 14 '10 at 7:27 bjarkef: right, I just answered to the part of auto-delete. Thomas Padron-McCarthy: agree, and this is written in my post.

– Alex Farber Apr 14 '10 at 7:30.

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