How to prevent “fat finger syndrome” in absence of req. predeclearation?

If your compiler does not provide a tool to spot these kind of troubles, you don't have much to hope for. I would recommend a very strict unit testing policy. At least it will make it easier to pinpoint the syndrome occurrence.

If your compiler does not provide a tool to spot these kind of troubles, you don't have much to hope for. I would recommend a very strict unit testing policy. At least it will make it easier to pinpoint the syndrome occurrence.

A possible (NB: possible) strategy is to take all the unique identifiers, one by line (e.g. Replace all spaces with returns) and then filter them through a sort | uniq. It will, hopefully, allow you to get a better view of strangely typed identifiers. You can also reduce such occurrence by using tab-completion in your editor.

Vim, for example, has a very useful function (Mosh_tab_or_complete) to perform autocompletion.

Adding a script to do something like sort | uniq sounds like a good idea. No identifier should only occur once in your code normally. What did you mean "(NB: possible)"?

The tab completion also sounds like a good idea, although I'm not a vim fan. (I wind up aborting out most of the time, cause I forget the keystrokes. ) – NoMoreZealots Aug 15 '09 at 20:48 I suggest you to add the -n switch to uniq, so to add the occurrence count.

The NB refers to the fact that if you have something like hello= 5 instead of hello = 5 you will get two identifiers "hello=" and "hello". This is not a big issue, you have to play with regexps a bit, but for a large codebase, and languages without distinction of keyword from identifier (e.g. Fortran) you cannot be 100 % sure. Fortran, however, has the IMPLICIT NONE directive, so it's not an issue, unless you have very old codes with so many implicit declarations to make the use of IMPLICIT NONE too time demanding.

– Stefano Borini Aug 15 '09 at 21:02.

Unit testing. Using TDD you write tests to define the expected behavior, then write the code to implement the behavior. Set up your expectations and mock objects then test that the mock objects had the correct methods called.

Check that your data now has the correct values.

HDLs are way ahead of software on this. You almost never compile before testing with simulation. (You can't exactly embed printfs in logic.) – NoMoreZealots Aug 15 '09 at 18:48.

Just remember to take it slow. Too many programmers rush and make mistakes like this. I know writing in Verilog is not very user friendly so you have to be extra careful in this case.

Yeah true. I like the syntax better than VHDL, but our HDL expert is leaning towards VHDL because it place and routes more consistenly. My opinion is both languages still need work.

– NoMoreZealots Aug 15 '09 at 19:15.

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