P6 Architecture - Register renaming aside, does the limited user registers result in more ops spent spilling/loading?

In addition to renaming registers to hide bubbles due to instruction latencies, most x86 architectures are smart enough to count pushes and pops and rename those onto registers as well. Remember that the instruction decoder on the x86 actually performs a sort of JIT compilation, turning the x86 instruction stream into a small microcode program stored in the trace cache. Part of this process includes intercepting small-offset stack loads and turning those into registers as well.

Thus something like (the patently silly and purely for example).

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