There is not enough information to say if there is a mistake in the implementation but I am guessing that there is a 1cycle delay because it is synchronous logic. Data changes and it sampled on the next clock edge therefore states appears to change 1 cycle after its input changed.
I cant really gove you an answer,but what I can give you is a way to a solution, that is you have to find the anglde that you relate to or peaks your interest. A good paper is one that people get drawn into because it reaches them ln some way.As for me WW11 to me, I think of the holocaust and the effect it had on the survivors, their families and those who stood by and did nothing until it was too late.