How much bandwidth is required to process a PECL or LVDS output?

The output signal swing is now halved. This can have phase noise or jitter implications for the receiving circuitry. It is important to note that the rise/fall time of the single-ended PECL output are not equivalent; generally the rise time is much smaller than the fall time.

If the receiving circuit uses the single-ended falling edge for critical timing this may be a problem. If I change the level of PECL output, does it affect the jitter? Yes, the slew rate of a clock signal can affect jitter.

The amount of jitter due to an input stage (receiver) is reduced by a faster slew rate at the input. A higher amplitude (signal voltage swing) can result in a faster slew rate. The amplitude of the AD9510/11/12 LVPECL outputs can be selected as 810 mV, 660 mV, 500 mV, or 340 mV.

The default swing is the highest, 810 ... more.

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