Xilinx, Isim treatment of Verilog integer types in simulation?

The result of any arithmetic or logical equality operation is 'x' if any of the operands are 'x'. Since it looks like I is not initialized, the statement I.

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I'm pretty new to FPGA and Verilog, but I'm having a problem getting my code to run in the simulator they way I would expect. It seems the Isim simulator is not "operating" on integers in my code. Below is a snippet of the relevant code.

I'm trying to divide the clk pulse by toggling SCK_gen every time integer I reaches 10. When I run this code in Isim, SCK_gen never changes value. Also it When I impliment the code on the FPGA, it behaves as I would expect, I can observe a pulse at 1/10 the clock frequency.

If anyone can point me in the right direction I'd be grateful. Thanks //signals //for SCK_clock reg SCK_gen, SCK_hold; integer i; reg en_SCK; wire neg_edge_SCK; //SCK_generator always @(posedge clk, posedge reset) if (reset) begin SCK_gen.

– Adam12 Mar 19 at 18:29 @Frank Dejay: please start accepting some Answers. – toolic Mar 20 at 16:42.

I figured part of this out right after I posted. I fixed this problem with an initial statement. So just to see if I got this right, if you don't specify an initial value to a reg or variable, then in the simulation it's value is x until assigned a value.

On the other hand though, when they are implemented in hardware they take a 0 value. Is this correct? Also should I comment out my initial statements before synthesis and implementation in hardware, or are those usually ignored?

– Frank Dejay Mar 19 at 20:28 Yes. Not always, this just happens to be the behavior of your tool chain and target hardware. The simulator has no way of knowing this from an RTL description therefore it marked the signal as unknown.

– Adam12 Mar 19 at 22:08.

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