Adder in verilog?
Register data types are used as variables in procedural blocks. A register data type must be used when the signal is on the left-hand side of a procedural assignment. Since the default type of ports is wire you get an error.
Changing your output ports to type reg should solve the problem.
Including the answer from @damage declaring the outputs as reg types, you also have CCR defined as 8 bits wide and then only assign the LSB.
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